The present invention pertains to apparatus and methods for surface planarization of metal surfaces. More specifically, it relates to electropolishing, electroetching and chemical etching technology for planarizing metal surfaces having low aspect ratio recesses or trenches as well as raised regions (bumps).
In the fabrication of integrated circuits, as the number of levels in an interconnect technology is increased, the stacking of additional layers on top of one another produces a more and more rugged topography. Without planarization, the microscopic canyons that result on the integrated circuit surface from stacking of device features create a topography that (1) would limit the resolution of photo-lithography and creation of dense feature patterns, and (2) would lead to defects in the integrated circuit that would make the circuit unusable.
One method of planarization used in the art is chemical mechanical polishing (CMP). CMP is a process that uses a mixture of abrasives and pads to polish the surface of the integrated circuit. Unfortunately, CMP polishing techniques are difficult to control; the endpoint can be difficult to detect. They are also expensive. The high equipment cost, waste handling cost, and low throughput contribute to the overall expense of CMP. Also, with the introduction of low-k dielectrics into chip production, modification of traditional CMP processes will be required, as current methods result in cracking and delamination of most low-k materials, which have a very low compression strength, and are extremely fragile.
Another method of planarization involves electrolytic etching technique such as electropolishing or electroless etching. These techniques are low cost methods, relative to CMP. Lower capital cost, easier waste handling, and much higher processing rates make it a desirable alternative to CMP. Electropolishing is a method of polishing metal surfaces by applying an electric current through an electrolytic bath, and removing metal via electrolytic dissolution. The process may be viewed as the reverse of electroplating.
A problem arises during the electropolishing of surfaces in which a large number of low aspect ratio (larger width than depth) features exist. Wide interconnect lines (trenches cut in a dielectric layer for a damascene process) and contact/bond pads often have low aspect ratios. Low aspect ratio features generally require the plating of an overburden layer slightly thicker than the thickness of the Damascene layer so that the feature will be completely filled after planarization. The metal fill profile above these features exhibits large recesses having profiles which resemble the original (low aspect ratio) feature. The metallization processes used to deposit the metal, which are substantially conformal over such low aspect ratio features, are typically not continued to a point which would geometrically xe2x80x9cclosexe2x80x9d such recesses, because to do so would require depositing a very thick metal layer. To do so would be uneconomical due to necessary removal of the large excess of metal at a later stage. Conventional electropolishing techniques can planarize a surface in which the recessed feature to be planarized is no more than perhaps three times as wide as it is deep. For features wider than these, the rate of removal is essentially uniform everywhere. When the metal layer is electropolished to the dielectric surface, recesses over low aspect ratio features are propagated and expanded to produce recesses that span the width of these features leaving effectively little or no metal in the pad regions. Obviously, this is an unacceptable result.
The current state of electropolishing technology has additional difficulties. For example, electropolishing typically requires highly viscous electrolyte baths (e.g., 85% phosphoric acid (H3PO4) in water, or with some added ethylene glycol). While these baths are effective in achieving good polishing and planarization rates, they make it difficult to remove defect-causing bubbles and to handle the fluids in general. Note that, depending on the electrolyte and tool design, a hydrogen generating reaction may take place at the cathode. The hydrogen can become entrained in the electrolyte, complicating tool design and presenting a potential safety hazard. In addition, these baths also have high resistivities, making for large power requirements and substantial amounts of generated heat (which must be removed to maintain a constant process control).
Mayer et. al. (U.S. patent application Ser. No. 09/412,837, filed Oct. 5, 1999, now U.S. Pat. No. 6,315,883,) describe a method of planarization of metal surfaces on wafers having both large and small recessed features by applying a film to the wafer surface prior to electropolishing. This film is applied in such a way that the film is thicker in the large feature recessed regions, and thinner over the substantially flat regions, and thinnest on exposed regions. This method allows differential electropolishing rates on different areas of the wafer such that planarization is achieved. While this technique is more effective with respect to conventional electropolishing approaches, the added application step can add cost to the operation, and may not sufficiently address planarization of raised regions (bumps) on the metal surface.
As mentioned, electroplating is a process that generally yields conformal deposition over low aspect ratio features and for the reasons described above, electroplating typically leaves large recessed areas over these type features. Additionally, it can be shown for conventional copper plating baths (i.e. not xe2x80x9csuperfillingxe2x80x9d baths) both theoretically and experimentally that high aspect ratio features (i.e. depth to width  greater than 3:1) are rapidly filled, and the metal above them becomes rapidly planarized. Using the electroplating methods mentioned above, small recessed areas exist in the metal fill profile over high aspect ratio features.
More commonly today however, electroplating bath additives are utilized to aid in the rapid xe2x80x9cbottom-upxe2x80x9d filling of higher aspect ratio features (e.g. in Damascene copper electroplating processes) to ensure homogeneous metal fill of these narrow features. Baths with xe2x80x9cbottom-upxe2x80x9d filling characteristics planarize smaller features much more rapidly than baths without such additives. In some cases (e.g. plating baths with superior bottom-up filling characteristic and no leveling additives) plating occurs at an accelerated rate after completing the small feature filling stage (see for example, xe2x80x9cA Superfilling Model that Predicts Bump Formationxe2x80x9d, A. C. West, S. Mayer, and J. Reid, Electrochemical and Solid State Letters, Vol. 4, No. 7, July 2001 and xe2x80x9cIntegration of Copper PVD and Electroplating Process for Damascence Feature Electrofilling, S. Mayer et. al., Interconnects and Contact Metalization for ULSI, Proceeding of the International Symposium, Electrochemical Society Inc., Volume 99-31, and xe2x80x9cFactors Influencing Damascene Feature Fill Using Copper PVD and Electroplatingxe2x80x9d, Solid State Technology, July, 2000, pg 86-103). When many high aspect ratio features are located in close proximity, a macroscopic raised area (series of bumps or a raised plateau) can be formed. This bump formation is also termed, xe2x80x9cfeature overplating.xe2x80x9d
Thus, use of advanced xe2x80x9cbottom upxe2x80x9d electrofill paradigms in combination with wafers having many low and high aspect features have created a problem of deposited metal surfaces having a range of topography to be planarized that is unusually large, i.e. containing both recessed and raised areas. Commonly, features that vary in size by two orders of magnitude on a single layer exist. A 1 xcexcm deep feature can have widths of from 0.2 xcexcm to 100 xcexcm. Therefore, while electroplating is a preferred method of metalization, various aspects of improved plating regimens create challenging topography for subsequent planarization.
What is needed therefore is improved electropolishing, electroetching and chemical etching technology for planarizing conductive layers having varying topography, particularly conductive layers having both recesses and raised regions having both very small (submicron) and very large (on the order of 100 micron) widths.
The present invention pertains to apparatus and methods for planarization of metal surfaces having both recessed and raised features, over a large range of feature sizes. The invention accomplishes this by increasing the fluid agitation in raised regions with respect to recessed regions. That is, the agitation of the electropolishing bath fluid is agitated or exchanged as a function of elevation on the metal film profile. The higher the elevation, the greater the movement or exchange rate of bath fluid. In preferred methods of the invention, this agitation is achieved through the use of a microporous electropolishing pad that moves over (either near or in contact with) the surface of the wafer during the electropolishing process.
Movement of the pad over the wafer surface can be combined with processes in which one xe2x80x9cmasksxe2x80x9d certain regions of a wafer surface with either xe2x80x9cdiffusion barriers.xe2x80x9d or xe2x80x9ckinetic barriersxe2x80x9d. Preferably, these barriers are selectively ablated by mechanical removal into the electropolishing pad.
Preferably, the diffusion barrier, acting as a mass transport xe2x80x9cmaskxe2x80x9d, is formed or placed on the wafer surface (by various means) prior to electropolishing and consists of a material of relatively low ionic conductivity and diffusivity. This effectively slows or blocks transport of metal ions produced during electroetching, electropolishing, or chemical etching. The diffusion barrier layer can be composed of various material types, but is generally of a substantially higher viscosity, by at least an order of magnitude, than the electropolishing, electroetching, or chemical etching electrolyte. In some cases the diffusion barrier is soluble in the electrolyte and in other cases the diffusion barrier is not soluble in the electrolyte. For each of these scenarios, a particular electropolishing pad is preferred.
For methods of the invention using electrolyte-soluble diffusion barriers, the electropolishing pad is preferably (but not necessarily) non-abrasive. For example a diffusion barrier film which is applied to the wafer is made of an electrolyte-soluble viscous liquid, and this is used in conjunction with a non-abrasive electropolishing pad.
For methods of the invention using electrolyte-insoluble diffusion barriers, the electropolishing pad is preferably (but not necessarily) abrasive. For example a diffusion barrier film which is applied to the wafer is made of an electrolyte-insoluble solid, and this is used in conjunction with a pad of sufficient abrasive properties to remove the insoluble film from the wafer""s exposed regions. In one embodiment, the pad should be sufficiently abrasive to break up the barrier film into small particles that can be removed from the surface region in the flowing electrolyte. In another embodiment, the abrasive electropolishing pad simply loads the removed diffusion barrier material internally in its pores. Alternatively, film material stored in the pore structure of the abrasive pad is periodically flushed out using a high fluid flow rate or a chemical that is a solvent for the insoluble film.
Electropolishing pads of the invention will be chemically compatible with the electrolyte (i.e. will not dissolve or otherwise break down). The pad will have a small pore size and be sufficiently porous to allow fluid and electrical current to easily flow through. A long-lived pad is also desirable, i.e. one that wears slowly.
In some methods, a diffusion barrier material is not added to the surface prior to electropolishing. In these methods the mechanical ability of the pad to thin or remove continually forming anodic surface films from exposed areas leads to an increased current density in those regions. The anodic films are preferentially dissolved away or mechanically removed from the wafer surface, via enhanced agitation of the electrolyte and/or the abrasive structure provided by the electropolishing pad. By selectively removing this film in the exposed regions, substantial differences in current density (and hence removal rate selectivity) is accomplished.
Thus, one aspect of this invention provides a method of electroplanarizing a metal layer disposed on a wafer surface, said metal layer having both recessed and raised regions on the field. Such methods may be characterized by the following sequence:(a) immersing the wafer holder into an electrolyte solution containing an electropolishing pad; (b) creating relative movement between the metal layer and the electropolishing pad; (c) bringing the wafer work surface and the electropolishing pad into proximity or contact with each other; (d) passing an anodic electrical current from the wafer through the electrolyte solution and to a cathode; and (e) stopping the passage of current at a point where all or a majority of the metal layer is removed from the field.
In a preferred embodiment we add the additional steps of selectively applying a diffusion barrier film to the recesses prior to performing electropolishing with the pad (prior to step (a) above). This process is particularly useful when the properties of the pad and polishing electrolyte are selected to remove diffusion layer material from the recesses more slowly than from the field regions. Any suitable process may be used to apply the diffusion barrier film. Preferably, the diffusion barrier film is applied in a manner that gives it a substantially planar surface. The degree of planarity of the diffusion barrier aids in the uniformity of the subsequent polishing process.
In cases where a solid or a very high viscosity non-ionically conducting diffusion barrier is added to the surface prior to electropolishing, one can remove the barrier from the field areas of the wafer selectively (for example by polishing with an abrasive pad) in a separate apparatus and thereby leave the barrier only in the recessed regions.
Another aspect of the invention is a method of electrochemically planarizing a metal layer deposited on a wafer. Such methods may be characterized by the following sequence: (a) applying a diffusion barrier film to a metal layer on the surface of a wafer; (b) removing the diffusion barrier film to expose only areas of highest elevation of the metal layer; and (c) electrochemically removing metal from the exposed regions of the metal layer until a newly defined field region is reached. Preferably (b) and (c) are repeated iteratively until a predetermined degree of planarization of the metal layer is achieved. Preferably (b) is achieved via mechanical removal with a polishing pad or via dissolving the uppermost portion of the diffusion barrier with a solvent.
Yet another aspect of the invention is an electropolishing apparatus for removing a portion of a metal layer disposed on a wafer. Such an apparatus may be characterized by the following elements: (a) a wafer holder for holding the wafer such that the metal layer is exposed; (b) a movement assembly configured to create relative movement between the metal layer and an electropolishing pad as well as positioning the metal layer""s work surface and the electropolishing pad""s work surface in proximity or contact with each other; and (c) an electropolishing cell containing the electropolishing pad and a cathode, both immersed in an electrolyte. Preferably during electropolishing, electrical current passes between the metal layer and the cathode through at least that portion of the electrolyte contained in a plurality of pores in the electropolishing pad. Also preferably, the wafer holder is configured to supply an anodic electrical current to the metal layer.
These and other features and advantages of the present invention will be described in more detail below with reference to the associated drawings.